The lift button that stays lit
Press the call button of a lift and take your finger off. The light stays on until the lift arrives.
Every circuit we have built so far (DRL, DTL, TTL, CMOS gates) is combinational: its output depends only on its inputs right now. Remove your finger, and the output forgets.
Today's question: what is the smallest circuit that remembers one bit?
Every bit of cache memory in your phone's processor is a 6-transistor cell: two cross-coupled CMOS inverters plus two access switches. Billions of today's latch, on one chip.
Feedback: the one idea behind all memory
- Combinational: output = f(present inputs). Sequential: output = f(present inputs, stored state).
- Two inverters in a ring: if v₁ is high, v₂ is low, which keeps v₁ high. Two self-consistent states, Q = 0 and Q = 1: a bistable circuit.
- There is a third consistent point, v₁ = v₂ = VM, but it is unstable: any imbalance is amplified round the loop (gain A > 1) until the circuit falls into one of the two stable states.
- A loop of inverters can hold a bit but has no way to be told a new one. Replace the inverters by NOR (or NAND) gates and the spare inputs become Set and Reset.
Gain is the whole story: the loop is bistable only if the inverters amplify (|slope| > 1 near VM). Two resistors in a ring remember nothing.
Live lab: the hilltop and the two valleys
Worked example: a transistor latch
Given
The fixed-bias binary in the figure. VCC = 12 V, VBB = 12 V, RC = 2.2 kΩ, R1 = 15 kΩ (collector to the other base), R2 = 100 kΩ (base to −VBB), hFE(min) = 30, VBE(sat) = 0.7 V, VCE(sat) = 0.2 V.
Find
Show that the state Q1 ON, Q2 OFF is self-consistent. Find VB2, VC2, IB1, IC1 and check that Q1 saturates.
Method: assume a state, then verify every transistor (Millman & Taub, the fixed-bias binary)
Solution
Predict the answer first. Then reveal one step at a time.
The SR latch: give the loop two handles
| S | R | Q next | Q̄ next | |
|---|---|---|---|---|
| 0 | 0 | Q | Q̄ | hold (memory) |
| 0 | 1 | 0 | 1 | reset |
| 1 | 0 | 1 | 0 | set |
| 1 | 1 | 0 | 0 | forbidden |
Two NOR gates, each output feeding the other's spare input. A 1 on any NOR input forces its output to 0: that is how S and R take control.
Active-low twin: the NAND S̄R̄ latch
A 0 on a NAND input forces its output to 1. So the inputs are active-low: S̄ = 0 sets, R̄ = 0 resets, S̄ = R̄ = 1 holds, and S̄ = R̄ = 0 is forbidden (Q = Q̄ = 1).
"Forbidden" is not about damage. With S = R = 1, Q and Q̄ stop being complements, and if both inputs are released together the next state is a race nobody can predict.
A set or reset pulse must last at least 2 tpd: one gate delay for the first gate to change, one for the second to answer and close the loop.
Live lab: set, reset, hold, and the race
| S | R | Q next | |
|---|---|---|---|
| 0 | 0 | Q | hold |
| 0 | 1 | 0 | reset |
| 1 | 0 | 1 | set |
| 1 | 1 | 0* | forbidden |
Worked example: reading a NOR latch timing diagram
Given
A NOR SR latch, initially Q = 0. Gate delays are neglected (each slot is long compared with tpd). The S and R waveforms are in the figure.
Find
Q and Q̄ for all 12 slots. Mark any slot where the latch is not in a valid state.
Method: hold / set / reset / forbidden, one slot at a time (Mano, SR latch)
Solution
Predict the answer first. Then reveal one step at a time.
Your turn · 1: the active-low latch
A NAND S̄R̄ latch starts with Q = 0. Draw Q and Q̄.
Work it out first.
Press Solve when the class has an answer.
Critical thinking · why is S = R = 1 really forbidden?
S = R = 1 just gives Q = Q̄ = 0, which is a perfectly definite output. So what exactly goes wrong?
Argue it in pairs for two minutes. There may be more than one defensible answer.
In the lab the race always ended. Could a real latch stay undecided for, say, a whole microsecond?
Argue it in pairs for two minutes. There may be more than one defensible answer.
Gated latches: listen only when enabled
- Put two NAND gates in front of an S̄R̄ latch, both driven by an enable C (often called the clock). C = 0: both front gates output 1, the latch holds. C = 1: S and R pass through.
- The gated SR latch still has a forbidden input (C = 1, S = R = 1).
- The D latch: feed S = D and R = D̄ through an inverter. S and R can never both be 1, so the forbidden input disappears.
Transparent
While C = 1 the D latch is a wire: Q follows D (one or two gate delays later). When C falls, Q freezes at the last value of D. That is what "latching" means.
The 74LS75 holds four D latches; two enables each control a pair. Processors used them to hold an address steady on the bus while the data moved.
Live lab: the transparent D latch
| C | D | Q next | |
|---|---|---|---|
| 0 | x | Q | hold (latched) |
| 1 | 0 | 0 | transparent |
| 1 | 1 | 1 | transparent |
Worked example: D latch timing
Given
A gated D latch, initially Q = 0. C and D as shown (gate delays neglected).
Find
Q for all 16 slots.
Method: C = 1 → copy D; C = 0 → hold
Solution
Predict the answer first. Then reveal one step at a time.
Your turn · 2: debounce a switch with a latch
A push button is an SPDT switch: contact A (normally closed) drives R̄, contact B drives S̄, both lines pulled up to 5 V. When pressed, the arm leaves A and bounces on B for a few ms.
(a) How many presses would a counter driven by the B line count? (b) Draw Q of an S̄R̄ latch. (c) Why does the latch remove the bounce? (d) Would it work with a two-terminal (SPST) button?
Work it out first.
Press Solve when the class has an answer.
Real world: alarms that must not forget
A pulse oximeter on a sleeping patient sees SpO₂ fall to 82 % for 20 seconds at 3 AM, then recover. The nurse was in another ward.
Medical alarm standards (IEC 60601-1-8) define a latching alarm: once triggered it keeps sounding after the cause has gone, until a person acknowledges it. In hardware, that is an SR latch: the comparator output drives S, the Acknowledge button drives R.
The same pattern appears in defibrillators ("shock advised" stays lit), infusion pumps (occlusion alarms) and ventilators. Memory turns a brief event into something a human can notice.
What should happen if the SpO₂ is still low when the nurse presses Acknowledge?
Argue it in pairs for two minutes. There may be more than one defensible answer.
Pop quiz
Question 1 / 5
A NOR SR latch has S = 0 and R = 0. Its output is…
Three things to remember
Feedback with gain makes a bistable: two stable states and one metastable balance point. A transistor latch: assume one ON, one OFF, then verify.
SR latch (NOR, active-high) and S̄R̄ (NAND, active-low): hold, set, reset, forbidden. Q⁺ = S + R̄Q, SR = 0.
Gated D latch: C = 1 transparent (Q follows D), C = 0 holds. No forbidden input, but every glitch on D gets through while C = 1.
A gated SR latch (built from NAND gates) starts with Q = 0. Draw Q.
Class Test 1 is in Week 5, Class 1 (Weeks 1–4, including next class's flip-flops). Assignment 1 is due the same day.
Work it out first.
Press Solve when the class has an answer.