CSE 2317 · W4 C2 · Flip-flops: edge-triggered memory

01 Cold open 0–4 min

The counter that counts wrong

Take last class's D latch, connect Q̄ back to D, and clock it. It should toggle once per clock: a divide-by-two, the first stage of every counter.

Instead, while the clock is high the new Q̄ races round the loop to D, through the transparent latch, back to Q̄… It toggles again and again, as many times as fit in the pulse.

Think deeper

How many times does the latch toggle in one clock pulse? What does it depend on?

Argue it in pairs for two minutes. There may be more than one defensible answer.

02 Live lab 4–8 min

Live lab: latch vs flip-flop, same feedback

Flip-flops: change only at the clock edge The dashed lines mark rising clock edges. A latch follows its input for the whole time the clock is high; a flip-flop looks only at the edge.

auto clock

Clock edges6

Latch toggles24

While CLK is high the latch is transparent: its new Q̄ reaches D after one delay and it toggles again, and again. How many times depends on the pulse width: useless as a counter.

03 Concept 8–13 min

Master–slave: two latches that never open together

Two D latches in series. The master is enabled by CLK̄, the slave by CLK.
CLK = 0: master open (follows D), slave closed (holds Q). CLK = 1: master closed (holds what D was), slave open (shows it).
At no moment is there an open path from D to Q. The value that gets through is the one D had at the 0 → 1 edge: a positive-edge-triggered D flip-flop.

Q^{+} = D \quad\text{(at the active clock edge)}

Pro tip

Read the symbol: triangle = edge-triggered; bubble + triangle = falling edge. No triangle = a latch (level-sensitive).

04 Live lab 13–18 min

Live lab: inside the master–slave D flip-flop

Flip-flops: change only at the clock edge The dashed lines mark rising clock edges. A latch follows its input for the whole time the clock is high; a flip-flop looks only at the edge.

auto clock

Q⁺ = D (sampled at the rising edge)

CLK = 0: master follows D, slave holds. CLK = 1: master holds, slave shows it. Toggle D while CLK is high and compare the two Q rows.

05 Worked example 18–24 min

Worked example: same D, latch vs flip-flop

Given

CLK and D as shown. A D latch (enabled by CLK = 1) and a positive-edge D flip-flop both start with Q = 0. Delays neglected.

Find

Q of the latch and Q of the flip-flop for all 16 slots.

Method: edges first, then the table (Mano: latch vs flip-flop)

Solution

Predict the answer first. Then reveal one step at a time.

06 Concept 24–29 min

SR, JK, D, T: four flip-flops, four equations

SR

00	Q
01	0
10	1
11	?

Q^{+} = S + \bar{R}Q

JK

00	Q
01	0
10	1
11	Q̄

Q^{+} = J\bar{Q} + \bar{K}Q

D

0	0
1	1

Q^{+} = D

T

0	Q
1	Q̄

Q^{+} = T \oplus Q

Characteristic tables (inputs → next state). The JK fixes SR's forbidden row by making it toggle; the T is a JK with J = K = T; the D is the simplest and the one used inside almost every chip.

Pro tip

The JK toggle row is only safe because the flip-flop is edge-triggered. A JK latch with J = K = 1 races around exactly like the opening demo.

07 Live lab 29–33 min

Live lab: JK and T

Flip-flops: change only at the clock edge The dashed lines mark rising clock edges. A latch follows its input for the whole time the clock is high; a flip-flop looks only at the edge.

auto clock

J	K	Q next
0	0	Q	hold
0	1	0	reset
1	0	1	set
1	1	Q̄	toggle

Q⁺ = J·Q̄ + K̄·Q

08 Worked example 33–38 min

Worked example: a JK timing diagram

Given

A positive-edge JK flip-flop, initially Q = 0. J and K change only while CLK is low (well away from the edges).

Find

Q for all 16 slots.

Method: read (J, K) at each rising edge only

Solution

Predict the answer first. Then reveal one step at a time.

09 Your turn 38–43 min

Your turn · 1: two T flip-flops make a counter

04:00

1 Exam CQ

Two negative-edge T flip-flops, both with T = 1, start at 0. CLK (10 MHz) drives the first; the first's output Q0 is the clock of the second.

Draw Q0 and Q1. What do Q1Q0 do as a 2-bit number? What are their frequencies?

Work it out first.
Press Solve when the class has an answer.

10 Worked example 43–48 min

Worked example: a JK flip-flop from a D flip-flop

Given

A positive-edge D flip-flop (Q⁺ = D) and any gates you need.

Find

Logic that makes it behave as a JK flip-flop.

Method: feed D with the target's characteristic equation (Mano, flip-flop conversion)

Solution

Predict the answer first. Then reveal one step at a time.

11 Your turn 48–51 min

Your turn · 2: convert

03:00

2 Exam CQ

Using any gates, convert: (a) a D flip-flop into a T flip-flop; (b) a JK into a D; (c) a JK into a T.

Work it out first.
Press Solve when the class has an answer.

12 Concept 51–55 min

Timing rules: setup, hold, clock-to-Q

Setup time t_su: D must be stable this long before the edge.
Hold time t_h: D must stay stable this long after the edge.
Clock-to-Q t_pcq (max) / t_ccq (min): how long after the edge Q changes.

\text{setup: } T_{clk} \ge t_{pcq} + t_{pd,\,logic} + t_{su}\qquad \text{hold: } t_{ccq} + t_{cd,\,logic} \ge t_h

74LS74-class D FF (approx.)
t_su	20 ns
t_h	5 ns
t_pcq (max)	25–40 ns
f_max (toggling)	≈ 25–33 MHz

Gotcha

Break setup or hold and the flip-flop is back on the hilltop of last class: metastable.

13 Worked example 55–59 min

Worked example: how fast can it run?

Given

Flip-flop A drives two gates in series, which drive flip-flop B (same clock). Flip-flops: t_pcq = 25 ns, t_ccq = 3 ns, t_su = 20 ns, t_h = 5 ns. Gates: t_pd = 15 ns max, t_cd = 3 ns min; the shortest path has one gate.

Find

The maximum clock frequency, and whether the hold time is met.

Method: setup and hold constraints (two-flip-flop path)

Solution

Predict the answer first. Then reveal one step at a time.

14 Live lab 59–64 min

Live lab: enter the forbidden window

Setup and hold: the forbidden window Slide the moment D changes. Outside the shaded window the flip-flop is predictable. Inside it, the output hangs halfway, for longer the closer you get to the balance point.

D changes at -3.00 ns relative to the clock edge

Flip-flop 1captured the NEW value (1)

2nd flip-flop (synchroniser)clean

15 Think deeper 64–68 min

Critical thinking · the button that crashes one board in a million

★ Critical thinking

A button, a sensor or another chip's signal is asynchronous: it can change at any moment, including inside the setup–hold window.

Take τ = 0.2 ns, T₀ = 0.1 ns, f_clk = 100 MHz and an input that changes 10⁶ times a second. Estimate the mean time between failures if the logic reads the flip-flop (a) 1 ns after the edge, (b) after a second flip-flop, ≈ 8 ns later.

Work it out first.
Press Solve when the class has an answer.

16 Real world 68–72 min

Real world: counting heartbeats

A heart-rate meter: an R-peak detector (comparator on the ECG) produces one pulse per beat, ≈ 80 ms wide. A counter of flip-flops counts the pulses during a gate window; the processor reads the count.

Edge-triggered, so each beat counts once however long the pulse lasts. A latch-based counter would race through several states during each 80 ms pulse.
Synchronised: the heartbeat has nothing to do with the 1 MHz clock, so the pulse first passes a two-flip-flop synchroniser, then an edge detector (Q₁ · Q̄₂) makes a one-clock-wide count enable.

BME corner

Bedside monitors, Holter recorders and smartwatches all do this, in hardware or firmware. A miscounted beat is not a cosmetic bug: arrhythmia detection depends on exact R–R intervals.

17 Pop quiz 72–76 min

Pop quiz

Score 0

Question 1 / 5

A positive-edge-triggered D flip-flop changes its output…

18 Recap 76–80 min

Three things to remember

A flip-flop samples at the clock edge (master–slave: two latches never open together). A latch is transparent for the whole level.

Q⁺: SR = S + R̄Q, JK = JQ̄ + K̄Q, D = D, T = T ⊕ Q. Convert by feeding the source's inputs from the target's equation.

Timing: T_clk ≥ t_pcq + t_logic + t_su; t_ccq + t_cd ≥ t_h. Asynchronous inputs: two-flip-flop synchroniser.

HW Before next class

Flip-flops: t_pcq = 12 ns, t_ccq = 4 ns, t_su = 6 ns, t_h = 3 ns. Between two of them: a longest path of 3 gates (8 ns each, max) and a shortest path of 1 gate (2 ns min).

(a) f_max? (b) Is hold met? (c) Is hold met for a direct flip-flop-to-flip-flop wire (a shift register)?

Class Test 1: next class (Week 5, Class 1), 20 minutes, Weeks 1–4. Assignment 1 is due at the start of the same class.

Work it out first.
Press Solve when the class has an answer.