CSE 2317 · W1 C2 · Adding a transistor: RTL to DTL

01 Cold open 0–5 min

The moon computer ran on one gate

The Apollo Guidance Computer (1969) was built from about 2,800 identical chips, each holding two 3-input NOR gates made of resistors and transistors.

One gate type. Every function. How?

Pop culture

The Lego approach: one brick shape, stacked cleverly, builds the whole Millennium Falcon. NOR is a brick that can build any logic function. Last class's diodes could not even make a NOT.

Think deeper

Draw a NOT gate using only one 2-input NOR. Then an OR.

Argue it in pairs for two minutes. There may be more than one defensible answer.

02 Live lab 5–15 min

The transistor as a switch (60-second refresher)

Transistor inverter Slide the input. A good switch lives in cutoff or saturation and dashes through the middle.

V_in = 0.00 V

β (h_FE) = 50 R_B = 10 kΩ

Cutoff · switch open

I_B = 0.000 mA · I_C = 0.00 mA

Cutoff

V_BE < 0.5 V. I_B ≈ I_C ≈ 0. Switch open, output high.

Active

$I_C=\beta I_B$ . Great for amplifiers, bad for logic.

Saturation

V_CE(sat) ≈ 0.2 V. Needs $I_B \ge I_{C(sat)}/\beta_{min}$ .

03 Worked example 15–21 min

Worked example: design the inverter

Given

V_CC = 5 V, R_C = 1 kΩ, R_B = 10 kΩ, β_min = 50, V_BE = 0.7 V, V_CE(sat) = 0.2 V.

Find

The minimum input voltage that saturates the transistor, and the overdrive factor at V_in = 5 V.

Method: Millman & Taub, transistor switch; Boylestad, BJT switching networks

Solution

Predict the answer first. Then reveal one step at a time.

04 Live lab 21–26 min

RTL: one transistor per input

RTL NOR: the Apollo gate Either input high saturates its transistor and pulls the shared collector low.

A	B	Y
0	0	1
0	1	0
1	0	0
1	1	0

I_B (high input)0.43 mA

I_C0.0 mA

Y = \overline{A + B}

Any high input saturates its own transistor and drags the shared collector low: NOR, the Apollo gate.

Gotcha

RTL's weak spot: an input only needs ≈ 0.5–0.7 V to start turning on, and a real "0" is already 0.2 V. Tiny low noise margin. DTL raises that threshold.

05 Concept 26–30 min

DTL NAND = diode AND + transistor NOT

Take last class's diode AND. Instead of using its output directly, feed it through two level-shifting diodes into a transistor inverter.

Pro tip

Every part has one job. Exam CQs love "state the function of D₁, D₂ and R₂".

R₁ + input diodes	The diode AND. Any low input steals R₁'s current.
D₁, D₂	Level shifters: each adds 0.7 V to what P needs to turn the transistor on → higher threshold, bigger noise margin.
R₂	Drains stored base charge so the transistor turns off fast; stops the base floating.
Transistor + R_C	The inverter: restores clean 0.2 V / 5 V and drives the next gates.

06 Live lab 30–36 min

DTL NAND, live

DTL NAND gate Flip A and B. Then pile on fan-out and lower β until the output low breaks.

Fan-out N = 4 β_min = 30

I1 through R10.56 mA

I R20.16 mA

I B0.40 mA

Must sink5.46 mA

β·IB available12.00 mA

Max fan-out11

Y = 0. Both inputs high, the transistor saturates with 2.2× the base drive it needs.

07 Worked example 36–43 min

Worked example: analyse the DTL NAND

Given

V_CC = 5 V, R₁ = R₂ = 5 kΩ, R_C = 2.2 kΩ, V_γ = 0.7 V, V_BE(sat) = 0.8 V, V_CE(sat) = 0.2 V, V_BE(cut-in) = 0.5 V, β_min = 30. Logic levels 0.2 V / 5 V.

Find

The output for (a) any input low and (b) all inputs high; check saturation.

Method: Millman & Taub / Taub & Schilling, DTL gate analysis

Solution

Predict the answer first. Then reveal one step at a time.

08 Worked example 43–48 min

Worked example: how many gates can it drive?

Given

The same gate, output low (Y = 0.2 V), driving N identical DTL gates.

Find

Maximum fan-out N.

Gotcha

Fan-out is decided in the low output state. When Y is high the driven gates' input diodes are reverse-biased and draw almost nothing.

Solution

Predict the answer first. Then reveal one step at a time.

09 Concept 48–52 min

Noise margin: why two level-shift diodes?

Noise margin = how much garbage a signal can pick up and still be read correctly. Low state: the input must stay below the voltage that starts turning the transistor on.

V_{th} = V_{P,on} - V_\gamma = 1.9 - 0.7 = 1.2\ \text{V},\quad NM_L = 1.2 - 0.2 = 1.0\ \text{V}

High state, roughly: input diodes stay off while V_in > V_P − V_γ = 1.5 V, so NM_H ≈ 5 − 1.5 = 3.5 V (unloaded).

Level-shift diodes	V_P to turn on	Input threshold	NM_L
0 (just the base)	0.5 V	≈ −0.2 V (fails!)	none
1	1.2 V	0.5 V	0.3 V
2 (course DTL)	1.9 V	1.2 V	1.0 V

10 Live lab 52–56 min

See a noise margin fail

Noise-margin scope Turn up the noise. Red ticks = the receiver read the wrong bit (or couldn't decide).

Noise amplitude ±0.60 V (peak ≈ 1.2 V)

NM low1.00 V

NM high3.50 V

Samples misread0 %

Errors start when the noise peak exceeds the smaller margin. A family is only as robust as its weaker side.

11 Your turn 56–60 min

Your turn · 1: cheap transistors

03:00

1 Exam CQ

In the course DTL NAND, replace the transistor with one whose β_min = 20. Everything else is unchanged.

What is the new fan-out?

Work it out first.
Press Solve when the class has an answer.

12 Your turn 60–63 min

Your turn · 2: a bigger R₂

2 Exam CQ

Change R₂ to 10 kΩ (β_min = 30). Find I_B and the fan-out.

What do you lose?

Work it out first.
Press Solve when the class has an answer.

13 Your turn 63–65 min

Your turn · 3: spot the wrong claim

3 Trap

A classmate says: "Fan-out is limited when the output is high, because the output must supply current to all the loads."

Is that right for DTL? Explain which state limits fan-out and why.

Work it out first.
Press Solve when the class has an answer.

14 Think deeper 65–68 min

Critical thinking · design for fan-out 10

4 Design

A customer needs the course DTL gate to drive 10 loads with β_min = 30. You may change only R_C.

What is the smallest R_C that works? Pick a standard value and state the trade-off.

Work it out first.
Press Solve when the class has an answer.

15 Think deeper 68–71 min

Critical thinking · then why not five level shifters?

5 Critical thinking

Two level-shift diodes gave NM_L = 1.0 V. A student proposes five diodes for an even bigger margin.

Analyse n = 3, 4, 5 (all else as the course DTL, β_min = 30). What goes wrong?

Work it out first.
Press Solve when the class has an answer.

16 Real world 71–74 min

Fan-out lives on in every board you build

An Arduino or Raspberry Pi pin has a current limit, exactly like our DTL collector. Hang too many LEDs or chip inputs on one pin and the "low" stops being low, or the pin is damaged. Datasheets still list the I_OL/I_IL currents fan-out is computed from (TTL version in Week 3).

BME corner

In a patient monitor one sensor signal may feed an ADC, a display driver and an alarm comparator at once. Every extra input loads the source and the reading drifts. The fix is DTL's idea: a buffer stage, so the fragile source drives only one input. The op-amp version (voltage follower) comes in Week 8.

17 Pop quiz 74–78 min

Pop quiz

Score 0

Question 1 / 5

In a BJT switch, the saturated collector current is set mainly by:

18 Recap 78–80 min

Three things to remember

A logic transistor lives in cutoff or saturation. Saturation needs I_B ≥ I_C(sat)/β_min.

DTL = diode AND + level-shift diodes + transistor NOT = NAND. Level shifters buy noise margin; R₂ buys speed.

Fan-out is set in the low state: 2.18 + 0.82N ≤ β_minI_B. Next week: switching speed and MOSFET gates.

HW Before next class

Same DTL gate but R_C = 4.7 kΩ (β_min = 30). Find the fan-out. Does a bigger R_C help or hurt when driving capacitive loads?

Work it out first.
Press Solve when the class has an answer.