CSE 2317 · W2 C2 · MOSFET switches and MOS gates

01 Cold open 0–4 min

15 billion switches, and your phone isn’t on fire

A current flagship phone chip holds roughly 15–20 billion transistors.

Pop culture

Doctor Strange checked 14,000,605 futures. Your phone's processor has about a thousand times more switches than that, and each one flips up to a few billion times per second.

Last class the BJT switch needed base current just to stay on. Multiply that by 15 billion.

Think deeper

Suppose every one of 15 billion switches leaked just 1 µA from a 1 V supply while idle. How much power is that?

Argue it in pairs for two minutes. There may be more than one defensible answer.

02 Concept 4–9 min

Enhancement NMOS: the gate builds its own wire

Structure: p-type substrate, two heavily doped n⁺ islands (source S, drain D), a thin SiO₂ insulator and a gate G on top. Metal–Oxide–Semiconductor.
V_GS = 0: S and D are two back-to-back pn junctions. No path, no current. Normally OFF (enhancement mode).
V_GS > V_T: positive gate charge pulls electrons to the surface and inverts it into a thin n-channel joining S to D. V_T is the threshold voltage (≈ 0.3–1 V on chips, 1–4 V in power MOSFETs).
The gate is a capacitor plate: in DC, I_G ≈ 0. The input is controlled by voltage, not current.

Pop culture

The channel is Hogwarts' Room of Requirement: it doesn't exist until you ask hard enough (V_GS > V_T), and the harder you ask, the bigger it gets.

03 Live lab 9–16 min

Grow a channel, then pinch it off

NMOS explorer: build a channel, then pinch it Raise V_GS past V_T to grow the channel; raise V_DS past V_GS − V_T to pinch it off at the drain.

V_GS = 3.00 V V_DS = 4.00 V V_T = 1.00 V k = 0.50 mA/V²

RegionSaturation · current source

I_D2.00 mA

V_GS − V_T2.00 V

r_DS(on) ≈ 1/[2k(V_GS−V_T)]500 Ω

04 Concept 16–21 min

Three regions, three equations

Region	Condition	Drain current
Cutoff	V_GS < V_T	$I_D = 0$
Triode	V_DS < V_GS − V_T	$I_D = k\left[2(V_{GS}-V_T)V_{DS} - V_{DS}^2\right]$
Saturation	V_DS ≥ V_GS − V_T	$I_D = k(V_{GS}-V_T)^2$

For a small V_DS drop the V_DS² term: the channel is a voltage-controlled resistor.

I_D \approx 2k(V_{GS}-V_T)\,V_{DS} \;\Rightarrow\; r_{DS(on)} \approx \frac{1}{2k(V_{GS}-V_T)}

Cutoffopen switch

Triodeclosed switch, r_DS(on)

Saturationcurrent source: only passed through while switching

Gotcha

Name trap. A saturated BJT is a closed switch. A saturated MOSFET is a current source (like BJT active). The MOSFET's closed-switch region is triode.

05 Worked example 21–27 min

Worked example: region and current

Given

Enhancement NMOS with k = 0.4 mA/V², V_T = 1.5 V.

Find

Region and I_D for (a) V_GS = 1 V, V_DS = 5 V; (b) V_GS = 4 V, V_DS = 5 V; (c) V_GS = 4 V, V_DS = 0.5 V. (d) r_DS(on) at V_GS = 4 V; compare with V_DS/I_D in (c).

Method: compute the overdrive, compare with V_DS, then pick the equation (Boylestad, enhancement MOSFET analysis)

Solution

Predict the answer first. Then reveal one step at a time.

06 Concept 27–30 min

Why MOSFETs won the switch war

	BJT switch (last class)	MOSFET switch
Controlled by	base current I_B	gate voltage V_GS
DC input current when ON	I_B ≥ I_C(sat)/β, all the time	≈ 0 (insulated gate)
ON voltage	V_CE(sat) ≈ 0.2 V, fixed	I_D·r_DS(on), can be millivolts
Turn-off delay	storage time t_s: excess minority charge	no storage time (majority carriers)
The catch	—	gate capacitance must be charged and discharged every switch

Gotcha

Zero DC gate current is not zero gate current. The gate is a capacitor: each transition needs a charge Q = C_G·ΔV delivered in a short time, which means a large transient current.

Remember t_s from last class, the BJT that refused to switch off? A MOSFET has nothing stored in a base to sweep out; its speed is set only by how fast you can move gate charge.

07 Think deeper 30–33 min

Critical thinking · “zero gate current”, so why a gate driver?

★ Critical thinking

A drone's motor controller uses a power MOSFET: total gate charge Q_g = 60 nC (at V_GS = 10 V), V_GS(th) = 2–4 V, switched by 20 kHz PWM.

A student connects it straight to a 3.3 V microcontroller pin (20 mA max): "MOSFETs draw no gate current, so it's fine."

Explain, with numbers, why the MOSFET gets hot and why engineers add a gate driver.

Work it out first.
Press Solve when the class has an answer.

08 Concept 33–37 min

The resistive-load NMOS inverter

V_in < V_T: MOSFET off, V_o = V_DD = V_OH.
Just past V_T: saturation, V_o = V_DD − R_Dk(V_in − V_T)², falling fast.
V_in high: triode, r_DS(on) ≪ R_D gives a small V_OL.

The edges of the "valid" input bands are where the curve's slope is −1: below V_IL and above V_IH noise is attenuated, between them it is amplified.

NM_L = V_{IL} - V_{OL}\qquad NM_H = V_{OH} - V_{IH}

V_DD = 5 V, R_D = 10 kΩ, k = 0.5 mA/V², V_T = 1 V: the next worked example.

09 Worked example 37–41 min

VTC part 1: V_OH, V_OL and V_IL

Given

Resistive-load NMOS inverter: V_DD = 5 V, R_D = 10 kΩ, k = 0.5 mA/V², V_T = 1 V.

Find

V_OH, V_OL, V_IL, and the static power with the output low.

Method: equate driver and load currents (Taub & Schilling, MOS inverter)

Solution

Predict the answer first. Then reveal one step at a time.

10 Worked example 41–45 min

VTC part 2: V_IH and noise margins

Given

Same inverter (a = kR_D = 5 V⁻¹). From part 1: V_OH = 5 V, V_OL = 0.124 V, V_IL = 1.1 V.

Find

V_IH, NM_L and NM_H.

Method: slope −1 by implicit differentiation, solved together with the VTC

Solution

Predict the answer first. Then reveal one step at a time.

11 Your turn 45–48 min

Your turn · 1: pick R_D

03:00

1 Exam CQ

Same MOSFET (k = 0.5 mA/V², V_T = 1 V), V_DD = 5 V, input high = 5 V.

The next stage needs V_OL ≤ 0.2 V. Find the minimum R_D, pick a standard E12 value, and give the static power when the output is low.

Work it out first.
Press Solve when the class has an answer.

12 Live lab 48–54 min

Swap the resistor for a transistor

A 10 kΩ on-chip resistor is huge, and slow: into 1 pF it rises in 2.2R_DC_L = 22 ns, while r_DS(on) = 250 Ω pulls down in ≈ 0.55 ns. Use a transistor as the load.

NMOS inverter lab Pick a load, slide V_in, then compare the noise margins and the static power when the output is low.

Resistor R_D from V_DD: the textbook starting point.

V_in = 0.60 V R_D = 10 kΩ

V_OH / V_OL5.00 / 0.124 V

V_IL / V_IH1.10 / 2.05 V

NM_L = V_IL − V_OL0.98 V

NM_H = V_OH − V_IH2.95 V

Static I (out low)488 µA

P = V_DD·I (out low)2.44 mW

13 Your turn 54–58 min

Your turn · 2: the enhancement-load inverter

2 Exam CQ

Enhancement-load NMOS inverter: V_DD = 5 V, both V_T = 1 V, driver k_D = 0.5 mA/V², load k_L = 0.05 mA/V². Ignore body effect.

Find (a) V_OH, (b) V_OL when V_in = V_OH, (c) the static power with the output low.

Work it out first.
Press Solve when the class has an answer.

14 Think deeper 58–60 min

Critical thinking · the load that gives up early

Think deeper

Why can the enhancement-load inverter never output the full 5 V, however long you wait?

Argue it in pairs for two minutes. There may be more than one defensible answer.

Think deeper

Same inverter, but k_D = k_L (ratio 1). What is V_OL? Why is NMOS called ratioed logic?

Argue it in pairs for two minutes. There may be more than one defensible answer.

15 Live lab 60–64 min

NMOS NOR and NAND: parallel or series

NMOS NAND / NOR lab Flip A and B. Current (and power) flows only when a path to ground exists. Compare the '0' of the two gates.

A	B	V_Y	Y	I (mA)
0	0	5.000 V	1	0.000
0	1	5.000 V	1	0.000
1	0	5.000 V	1	0.000
1	1	0.245 V	0	0.475

r_DS(on) each250 Ω

P now2.38 mW

Two in series ≈ 500 Ω. V_OL = 0.245 V, double a lone inverter's 0.124 V. Try W/L 2×.

16 Your turn 64–67 min

Your turn · 3: the price of series transistors

3 Exam CQ

Two-input NMOS NAND: R_D = 10 kΩ, V_DD = 5 V, each pull-down k = 0.5 mA/V², V_T = 1 V, A = B = 5 V.

Estimate V_OL, compare it with a single inverter, and find the k (W/L) each transistor needs to restore the inverter's V_OL.

Work it out first.
Press Solve when the class has an answer.

17 Think deeper 67–69 min

Critical thinking · NAND or NOR?

★ Trap

A classmate's notes say: “NAND is always preferred over NOR, in every logic family.”

Is that true for NMOS logic? Does your answer change for CMOS? Justify with what you saw in the gate lab.

Work it out first.
Press Solve when the class has an answer.

18 Concept 69–72 min

The NMOS power tax, and the CMOS escape

Every NMOS gate with its output low draws $P = V_{DD}\cdot I$ continuously. Our inverter: 2.44 mW.

One million such gates, half of them low: 1 × 10⁶ × 0.5 × 2.44 mW ≈ 1.2 kW. This is why NMOS chips of the late 1970s ran warm with only tens of thousands of transistors.

CMOS pairs a PMOS pull-up with an NMOS pull-down on the same input. In either steady state one of them is off, so there is no path from V_DD to ground: static current ≈ leakage only, V_OH = V_DD, V_OL = 0.

Pro tip

Try the CMOS tab in the inverter lab: full 0–5 V swing, a symmetric VTC, and static power ≈ 0. Power is now spent only while switching. Next week: CMOS in depth, plus TTL, ECL and I²L.

19 Real world 72–75 min

A MOSFET that makes a battery last a month

A finger pulse oximeter or an ECG patch has an analog front end and LEDs that draw a few mA. A MOSFET load switch between the battery and that circuitry turns it on only while measuring: power gating.

220 mAh cell	Average current	Battery life
Front end always on (3 mA)	3 mA	≈ 73 h (3 days)
Gated: on 10 % + 5 µA sleep	0.305 mA	≈ 721 h (30 days)

A switch with r_DS(on) = 50 mΩ drops only 3 mA × 50 mΩ = 0.15 mV: the sensor never notices it is there.

BME corner

For a community health worker screening children for pneumonia (low SpO₂) in a rural upazila, a device that runs a month between charges is the difference between used and abandoned. Every wearable ECG and glucose monitor uses the same trick.

Drone corner

A quadcopter, like the student-built drones flown at Bangladeshi university robotics fests, spins each motor with an ESC: an H-bridge (or 3-phase bridge) of power MOSFETs at tens of kHz, each with a gate driver, exactly the design from slide 7.

20 Pop quiz 75–78 min

Pop quiz

Score 0

Question 1 / 5

An NMOS has V_T = 1 V, V_GS = 3 V and V_DS = 1 V. It is in…

21 Recap 78–80 min

Three things to remember

V_GS > V_T builds the channel. Triode (V_DS < V_GS − V_T) is the closed switch, r_DS(on) ≈ 1/[2k(V_GS − V_T)]. Saturation is a current source.

NMOS inverter: V_IL, V_IH at slope −1; NM_L = V_IL − V_OL, NM_H = V_OH − V_IH. Enhancement load: V_OH = V_DD − V_T, ratioed.

NOR = parallel, NAND = series (needs n× W/L). Output low = static power V_DD·I. CMOS removes it: next week.

HW Before next class

A 3.3 V resistive-load NMOS inverter: R_D = 20 kΩ, k = 0.25 mA/V², V_T = 0.7 V. Find V_OL, V_IL, V_IH, both noise margins and the static power with the output low. Check each region.

Work it out first.
Press Solve when the class has an answer.

MOSFET switches and MOS gates

15 billion switches, and your phone isn’t on fire

Enhancement NMOS: the gate builds its own wire

Grow a channel, then pinch it off

Three regions, three equations

Worked example: region and current

Given

Find

Solution

Why MOSFETs won the switch war

Critical thinking · “zero gate current”, so why a gate driver?

The resistive-load NMOS inverter

VTC part 1: VOH, VOL and VIL

Given

Find

Solution

VTC part 2: VIH and noise margins

Given

Find

Solution

Your turn · 1: pick RD

Swap the resistor for a transistor

Your turn · 2: the enhancement-load inverter

Critical thinking · the load that gives up early

NMOS NOR and NAND: parallel or series

Your turn · 3: the price of series transistors

Critical thinking · NAND or NOR?

The NMOS power tax, and the CMOS escape

A MOSFET that makes a battery last a month

Pop quiz

Three things to remember

VTC part 1: V_OH, V_OL and V_IL

VTC part 2: V_IH and noise margins

Your turn · 1: pick R_D