The supercomputer that needed a refrigerator
The Cray-1 (1976), the fastest computer of its day, ran at 80 MHz. It was built from about 200,000 ECL gates and drew around 115 kW, with Freon cooling pipes running through the frame.
A phone today does thousands of times more work on a few watts, with CMOS. Between them sits a third idea, I²L, that packed bipolar logic tighter than anything before it.
Why would anyone accept 115 kW of heat for 80 MHz? What was the alternative in 1976?
Argue it in pairs for two minutes. There may be more than one defensible answer.
ECL: steer a current, don't switch it
- A differential pair: input transistor(s) and a reference transistor at VR = −1.3 V share one emitter resistor RE, which sets a roughly constant current (≈ 4 mA).
- Input above VR: the current goes through the input side. Below: through the reference side. A few hundred mV move all of it.
- The collector resistors are small, so the collectors never fall low enough to saturate anything: no stored charge, no ts.
- Emitter followers buffer both collectors: low output resistance, and you get OR and NOR outputs from every gate.
Why the odd supply?
VCC = 0 V (ground) and VEE = −5.2 V. The outputs are measured from the ground rail, which is the quietest node on the board. Logic levels: about −0.9 V (1) and −1.75 V (0).
Extra inputs are just more transistors in parallel with the input transistor: any input above VR steers the current. So the gate is naturally OR / NOR.
Live lab: watch the current move
Total stays ≈ 4 mA: the supply sees no spike when the gate switches.
Worked example: an ECL OR/NOR gate
Given
VCC = 0, VEE = −5.2 V, VR = −1.3 V, RE = 780 Ω, RC1 = 220 Ω (NOR side), RC2 = 245 Ω (OR side). VBE = 0.75 V for every conducting transistor (followers included). Neglect base currents.
Find
IE, VOR and VNOR for A = −1.75 V and for A = −0.75 V. Check that the input transistor does not saturate.
Method: find which transistor has the higher base, set VE from it, then IE (Millman & Taub, ECL analysis)
Solution
Predict the answer first. Then reveal one step at a time.
ECL: what speed costs
| ECL 10K | 74 TTL | |
|---|---|---|
| Delay | ≈ 2 ns | ≈ 9 ns |
| Power per gate | ≈ 25 mW, constant | ≈ 10 mW |
| Logic swing | ≈ 0.85 V | ≈ 3.4 V |
| Noise margins | ≈ 0.13–0.15 V | 0.4 V |
| Supply current when switching | nearly constant | 30 mA spikes |
| Outputs | OR and NOR, both | one |
Small swing = less charge to move = fast. But small swing also means small noise margins. ECL boards need careful layout: 50 Ω transmission lines, terminations, ground planes.
Constant current is a hidden advantage: the supply sees no spikes, so ECL generates far less switching noise than TTL.
Your turn · 1: redesign the ECL gate
The ECL gate is redesigned with RE = 1.18 kΩ and RC1 = RC2 = 300 Ω. Everything else as in the worked example (VR = −1.3 V, VEE = −5.2 V, VBE = 0.75 V).
Find IE, VOR and VNOR for both input levels, check for saturation, and comment on power and speed.
Work it out first.
Press Solve when the class has an answer.
I²L: logic with no resistors at all
- Each gate is one multi-collector NPN (run upside down: emitter at ground) fed by a PNP current injector that acts as a constant current source into its base.
- Input LOW (another gate pulls the base down): the injector current is diverted, the NPN is off, its collectors float (read as 1). Input open: the injector current turns the NPN on, collectors pull low (0). It is an inverter.
- No resistors, and the PNP shares regions with the NPN, so a gate takes about the area of one transistor. Swing ≈ 0.6 V (0.1 V to 0.7 V).
- Speed and power are set together by the injector current: double it, and the gate is about twice as fast and uses twice the power (constant speed–power product, ≈ 1 pJ or less).
Texas Instruments built a bipolar version of its TMS9900 microprocessor in I²L (the SBP9900) for harsh-temperature use: I²L packed a whole CPU into bipolar technology.
Your turn · 2: wiring collectors makes NOR
Two I²L inverters have inputs A and B. One collector of each is wired to the same node Y, which feeds the base of the next gate (supplied by its own injector).
Write Y as a function of A and B. How would you make A + B?
Work it out first.
Press Solve when the class has an answer.
CMOS: one switch up, one switch down
- A PMOS from VDD and an NMOS to ground, gates tied together. Input 0: PMOS on, NMOS off, output = VDD. Input 1: the reverse, output = 0 V.
- In either steady state one transistor is off: no static current (leakage only), VOH = VDD, VOL = 0. Full rail-to-rail swing.
- Current flows only while switching: to charge and discharge the load, plus a short "both on" burst near VM.
Matched inverter (kn = kp, equal |VT|)
Noise margins: NML = NMH = (3VDD + 2VT)/8.
Electrons are ≈ 2–3× more mobile than holes. Equal-size transistors are not matched: the PMOS must be about 2.5× wider.
Live lab: the CMOS inverter
Worked example: the matched CMOS inverter, then the unsized one
Given
CMOS inverter, VDD = 5 V, VTn = |VTp| = 1 V, kn = kp = 0.5 mA/V² (square law, ID = k(VGS − VT)² in saturation).
Find
VM, VIL, VIH, both noise margins and the peak supply current. Then VM if both transistors have the same W/L (µn = 2.5 µp).
Method: symmetric-inverter formulas (Taub & Schilling, CMOS inverter)
Solution
Predict the answer first. Then reveal one step at a time.
Live lab: CMOS NAND and NOR
| A | B | pull-up | pull-down | Y |
|---|---|---|---|---|
| 0 | 0 | ON | off | 1 |
| 0 | 1 | ON | off | 1 |
| 1 | 0 | ON | off | 1 |
| 1 | 1 | off | ON | 0 |
In every row exactly one network conducts: the output is always driven, and there is never a path from VDD to ground. Static current ≈ leakage only.
The networks are duals: series in one ↔ parallel in the other. The NAND's series stack is NMOS (fast electrons): cheap to size up.
CMOS is not free: P = αCV²f
Every 0 → 1 transition takes energy CLVDD² from the supply (half is stored in the load, half burned in the PMOS; the stored half is burned in the NMOS on the way down).
α = activity factor (the fraction of clock cycles in which a node switches), CL = switched capacitance, f = clock frequency.
| One 74HC output, 50 pF load, α = 1 | P |
|---|---|
| 5 V, 1 MHz | 1.25 mW |
| 3.3 V, 1 MHz | 0.54 mW |
| 5 V, 10 MHz | 12.5 mW: more than a standard TTL gate |
Three knobs: lower V (squared!), lower f when idle, switch less (α: clock gating). Your phone's processor turns all three every millisecond (dynamic voltage and frequency scaling).
At nanometre scales, leakage (static current through "off" transistors) is no longer negligible: billions of small leaks. Modern chips power-gate whole blocks off.
Your turn · 3: the power budget of a chip
A microcontroller switches an effective capacitance of 2 nF with activity factor α = 0.15.
(a) Dynamic power at VDD = 1.8 V, f = 100 MHz? (b) In low-power mode it runs at 1.2 V and 50 MHz. New power? How much of the saving comes from the voltage?
Work it out first.
Press Solve when the class has an answer.
Critical thinking · never let a CMOS input float
Last class a floating TTL input read as HIGH. What happens to a floating CMOS input, and why is it worse?
Argue it in pairs for two minutes. There may be more than one defensible answer.
Latch-up: the n and p regions of a CMOS chip form a parasitic thyristor (PNPN). A voltage spike on a pin can trigger it into a short from VDD to ground that only power-cycling clears. Keep input voltages within the supply rails.
Live lab: every family on one chart
ECL 10K
Non-saturating current switch, −5.2 V supply, 0.85 V swing, NM ≈ 0.15 V.
CMOS power = (Cpd + 15 pF)·V²·f: slide the frequency and watch only the CMOS dots move.
Real world: ten years on one battery
An implanted cardiac pacemaker senses every heartbeat and fires when one is missed, for 8–10 years on a single lithium battery that cannot be recharged.
Sensing amplifiers, the timing logic and the pacing pulses all fit inside about 17 µA. Only CMOS, mostly idle and clocked slowly at a low voltage, can do that. Built from standard TTL, the logic alone would need milliamps: the battery would last days.
The same logic applies to hearing aids, continuous glucose monitors and capsule endoscopes. In implant design the question is never “how fast?” but “how many joules per decision?”: the speed–power product from today's chart.
Why is a pacemaker's clock often only tens of kHz, when the chip could run at MHz?
Argue it in pairs for two minutes. There may be more than one defensible answer.
Pop quiz
Question 1 / 5
The main reason ECL is faster than TTL is that its transistors…
Three things to remember
ECL steers a constant current (VR = −1.3 V): no saturation, ≈ 1–2 ns, OR + NOR outputs, but ≈ 25 mW constant and ≈ 0.15 V margins.
I²L: injector current source + multi-collector NPN, no resistors, densest bipolar logic; wired collectors give NOR.
CMOS: no static current, rail-to-rail, NM ≈ (3VDD + 2VT)/8 when matched (PMOS ≈ 2.5× wider). Power = αCV²f.
A matched CMOS inverter runs from VDD = 3.3 V with VT = 0.7 V. Find VM, VIL, VIH and the noise margins. It drives 30 pF and toggles every cycle at 20 MHz: dynamic power?
Assignment 1 covers this week (TTL, ECL, I²L, CMOS): due Week 5, Class 1.
Work it out first.
Press Solve when the class has an answer.